1. Technical Field
Embodiments of the present invention relate to a test mode signal generating device, and more particularly, to a test mode signal generating device capable of generating a test mode signal by using an address signal, so that a semiconductor apparatus can perform a test operation.
2. Related Art
In general, to ensure a reliability of a semiconductor apparatus, various tests are performed during a manufacturing process or before shipping products. Since there are various performance tests to be conducted on the semiconductor apparatus, the testing involves setting a plurality of test modes in which the various performance tests are performed and performing the various tests on the semiconductor apparatus based on the predetermined test modes. In general, the semiconductor apparatus logically combines address signals to generate a test mode signal that can instruct the semiconductor apparatus to enter into a specific test mode.
FIG. 1 is a block diagram schematically showing a configuration of a conventional test mode signal generating device. The test mode signal generating device of FIG. 1 includes a control unit 10, an address decoder 20, and a test mode signal generating unit 30. The control unit 10 receives address signals MREG<0:6>, a normal MRS signal NMRSP, a test MRS signal TMRSP, and a power-up signal PWRUP. The control unit 10 generates transfer address signals TMREG<0:6> in response to the address signals MREG<0:6> when the test MRS signal TMRSP is enabled. The control unit 10 generates a reset signal TRSTPB by using the normal MRS signal NMRSP and the power-up signal PWRUP. The address decoder 20 decodes the transfer address signals TMREG<0:6> input from the control unit 10 and then generates test address signals TRG01<0:3>, TRG234<0:7> and TRG56<0:3>. The test mode signal generating unit 30 receives the test address signals TRG01<0:3>, TRG234<0:7> and TRG56<0:3> to generate a test mode signal TM. The test mode signal generating unit 30 includes a plurality of signal generating units 31, 32, 33 and 34 and generates a plurality of test mode signals TM. The test mode signals ‘TM’ are different from one another in their number of logic combinations of the test address signals TRG01<0:3>, TRG234<0:7> and TRG56<0:3>.
FIG. 2 is a diagram showing a configuration of one of the plurality of signal generating units 31 to 34 constituting the test mode signal generating unit 30 of FIG. 1. As shown in FIG. 2, the signal generating unit 31 includes first to third NMOS transistors Na to Nc, a first PMOS transistor Pa, and first to third inverters IVa to IVc. The first to third NMOS transistors Na to Nc receive test address signals TRG01<0>, TRG234<m> and TRG56<n> assigned to them through their gate terminals, respectively, where m is an integer greater than or equal to 0 and less than or equal to 7, and n is an integer greater than or equal to 0 and less than or equal to 3. The first PMOS transistor Pa receives the reset signal TRSTPB through its gate terminal. The assigned test address signals TRG01<0>, TRG234<m> and TRG56<n> determine whether the first to third NMOS transistors Na to Nc are turned on or not, respectively, and the first to third NMOS transistors Na to Nc apply a ground voltage VSS to a node C when the first to third NMOS transistors Na to Nc are all turned on. The first PMOS transistor Pa is turned on to apply an external voltage VDD to the node C when the reset signal TRSTPB is enabled at a logic low level. The first and second inverters IVa and IVb latch a voltage level of the node C, and the third inverter IVc outputs an inverted signal of the voltage level of the node C as the test mode signal TM. The signal generating unit 31 turns the node C to the ground voltage (VSS) level to enable the test mode signal TM when the assigned test address signals TRG01<0>, TRG234<m> and TRG56<n> are enabled. The signal generating unit 31 turns the node C to the external voltage (VDD) level to disable the test mode signal TM when the reset signal TRSTPB, which indicates an end of the test operation, is enabled.
All of the signal generating units of the test mode signal generating unit 30 have substantially the same configuration as that of the signal generating unit 31 of FIG. 2. In other words, all of the remaining signal generating units 32, 33, and 34 have substantially the same configuration as that of the signal generating unit 31 of FIG. 2.
In general, the address signals are input into the semiconductor apparatus through pads, and the number of input address signals used to generate the test mode signals is limited. For example, if seven input address signals are used to generate the test mode signal, the test mode signals that can instruct the semiconductor apparatus to enter into 128 different test modes can be generated. In this case, the number of the signal generating units will be 128.
In general, the semiconductor apparatus performs the various tests through various test modes in order to improve the reliability of product. However, since the number of address signals used to perform the test is limited, it is difficult to generate a greater number of test mode signals.